| | Standard Course Syllabus | Course Supervisor | Date of Approval |
| | Dept. of Electrical and Computer Engineering | DeGroat | 5/05 |
| | 764 | Functional Verification of Hardware Designs |
| | 2. | CATALOG DESCRIPTION |
| | Techniques for verification of hardware designs; writing testbenches; verification of increasingly complex computer circuit |
| | designs provided by industry using simulation environments used in industry. |
| | Quarters of Offering | Credits | | Level | Class Meeting |
| | Sp Qtr. | 3 | U G | 2 cl, 1 3-hr lab |
| | Course Prerequisites |
| | Prereq: 762. |
| | 3. | PREREQUISITES BY TOPIC |
| | Digital hardware design, computer architecture, basic knowledge VHDL or Verilog, familiarity with running a simulation |
| | Courses that require this as a direct prerequisite |
| | none |
| | 4. | Text(s) and Other Course Materials | Author(s) | Publisher |
| | Writing Testbenches: Functional Verification of HDL | Bergeron, J. | Kluwer |
| | Models, 2nd Ed. |
| | References (supplemental reading) |
| | 5. | COURSE OBJECTIVES |
| | 1. Students will learn to plan and carry out an effective functional verification of a design. (Criteria 3(c),(e),(g),(k)) |
| | 2. Students will learn to use verification tools and experiment on actual circuits designed in industry. (Criteria 3(c),(e),(k)) |
| | 3. Student will learn to work in teams to debug designs. (Criterion 3(d)) |
| | 6. | TOPICS AND (# OF LECTURES) |
| | Introduction, verification approaches (1) |
| | Industry perspective (1) |
| | Verification tools, simulators (2) |
| | Verification plan; levels of verification, verification strategies (3) |
| | Stimulus and response; self-checking testbenches (2) |
| | Architecting testbenches (1) |
| | Simulation management, behavioral models (1/2) |
| | Formal verification (1/2) |
| | Assertion based verification (4) |
| | PSL - the assertion language (4) |
| | Student presentations (1) |
| | Projects: |
| | 1. A design and testcases will be given for a project, such as a calculator. Students will debug. (2 weeks) |
| | 2. Pipelined ALU. Students will come up with verification plan, test case and run simulation and find bugs. (2 weeks) |
| | 3. Simple cache: Introduce randomization. (2 weeks) |
| | 4. Verify a big example. (4 weeks) |
| | 7. | CLASS MEETING PATTERN | (For example, "3cl." means 3 48-min classes per week.) |
| | 2 cl, 1 3-hr lab |
| | Thursday, August 14, 2008 09:21 AM |
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