|
| Design Projects | Facilities | | Search | |
|
| MISES | Cadence | Links | | Publications | |
|
| Design Projects | Facilities | | Search | |
|
| MISES | Cadence | Links | | Publications | |
Some Notes on Mixed Signal Simulation Basics in Cadence...
by John Sheridan Fisher
Documentation on doing analog/mixed-signal (AMS) simulations in Cadence are available at:
First things first... only simulate in true AMS mode if necessary. The analog-to-digital interface elements use a large amount of simulation processing. In addition, attempting to force a mixed-mode simulation when only analog parts or only digital parts are present usually fatally confuses the simulator (since it does not know where to put the interface elements) and is difficult to circumvent. Specifically, when modeling an analog only device, use a 'veriloga' view not a 'verilogams' view, and when modeling a digital only device, use a 'verilog' view not a 'verilogams' view. Then, judiciously use (the parameters of) the interface elements to connect these components together in higher level simulations.
However, when modeling a truly mixed signal component (i.e. A/D, D/A) a 'verilogams' view is entirely appropriate. Still, consider if the simulation time hit is appropriate. For example, a flash A/D can have a bank of comparators, whose 'digital' output is read by a digital thermo-code decoder. These 'digital' outputs are, of course, actually analog values from the comparators that could be easily modeled in a pure 'veriloga' view. The comparator model does not have any real need for the digital modeling aspect of a 'verilog' view, so using a 'verilogams' view for this flash A/D would push the interface elements into this lower level cell unnecessarily and may cause a poorer automatic selection of interface element configurations by the simulator. Further, 'verilogams' views are unlikely to synthesize in any manner, so use them judiciously.
The a priori AMS simulation requirements can be found in the Mixed-Signal Interface -> Design Details section of:
The critical portion of working with AMS simulations has to do with the interface elements, which connect analog-to-digital. A good theoretical discussion on the topic of how interface elements effect a simulation is given at in the Mixed-Signal Aspects of VerilogAMS -> Connect Modules section of:
While this section gives good coverage of the trade-offs of partitioning a design in various manners, it does not give any useful insight into how to actually insert/modify the interface elements. In contrast, the document:
gives a good tutorial on how to place the interface elements and modify the partitioning of the design, but does not have any useful insight as to why or what method would be good to follow. Using these two sections in tandem should illuminate both the whys and hows of using interface elements.
Having said all of that, interface elements will automatically be placed by the simulator on a best effort (for simulation optimization) basis by the simulator/netlister. Using SpectreVerilog or the AMS Simulation Environment, the netlister will automatically partition the design, assuming that there are both analog and digital elements. It is important to reiterate that the netlister will attempt to insert interface elements into the design if a 'verilogams' view is used and will fatally fail unless both analog and digital sections are found. If the automatically inserted interface elements are unacceptable, use the aforementioned documentation to optimize the placements [proceed with peril].
Even with automatic placement, general configuration of the interface elements will usually be needed. Specifically, the default (assumed) power rails for the analog-to-digital interface is 0V to 5V. When simulating in SpectreVerilog, these values are easily changed for the system under test in the testbench schematic editor.
*** We have not yet determined how to change the parameterization of the interface modules used in the AMS Environment, which is an ugly action item for this tutorial in the future. As a stopgap measure, a veriloga wrapper module (interface element) can be used to transfer the digital voltage I/O levels to the appropriate range. Also, the MGC ADV_MS simulator has its own interface element system.
For SpectreVerilog, once a 'config' view has been created with the Hierarchy Editor, the interface elements can be configured. In the testbench schematic window (opened through the 'config' view), if there is no 'Mixed-Signal' menu header, then select the Tools -> Mixed Signal Opts. item; now under the 'Mixed-Signal' menu header will be available. Select Mixed-Signal -> Interface Elements, and note the five options to change interface element properties.
The 'Library' option will access the entire design library's default options. Changes made in this form will be saved to the library's prop.xx file/bag and affect every design in the library, unless overridden at the cell or instance level.
The 'Cell' option will ask for a particular cell to be selected. Once selected, the cell's 'symbol' view will be opened for edit and its interface element properties can be modified. In particular, every instance of the cell will inherit these changes as its default parameters, overriding any library defaults (unless overridden for at particular instance). These changes are saved in that symbol's database, and can be reviewed at any time while within the symbol editor by viewing the cellview properties (hotkey 'Q') of that symbol.
Very similarly, the 'Cell Terminal' option will ask for a particular cell's terminal to be selected. Once selected the symbol editor will again open, but will allow the modification of the interface element properties of that selected terminal only. These changes are also saved to that symbol's database and are in its cellview properties.
The 'Instance' option will ask for a particular instance within the schematic to be selected. Once selected, the interface element properties form will allow for modification of only that instance's properties. Changes made here are saved in the schematic's database.
Very similarly, the 'Instance Terminal' option allows for the modification of the properties of a single terminal on a single instance in the schematic.
The order of precedence (from highest to lowest) is understood to be: Instance Terminal, Instance, Cell Terminal, Cell, Library, system default. The document:
describes the effect of modifying each of the fields of the IE Model Property Editor. Suffice to say that analogLib contains a MOS-type load/drive model for analog-to-digital and digital-to-analog interfaces, as well as the complement for TTY. Generally, only the model parameters need be altered. We recommend correcting the output model's rise-time, fall-time, logic '1' voltage, and logic '0' voltage for the system under test, as well as the input model's logic '0' voltage trip point and logic '1' voltage trip point [a2d_tx is the length of time an input signal is allowed to stay between a2d_v0 and a2d_v1 before being declared an 'X' state.]
[A paragraph about underlying mechanics...] Also, since the form is just a convenient lever to modify symbol and instance properties, the appropriate property name/value pair could be directly added to any symbol/instance through the cellview/object properties window. Perhaps of more interest, if a given cell has interface element properties, when it is used in a schematic, its object properties will show the cell's interface element parameters with master (default cell) value, as well as a space for a local (instance) value; the instance parameters can be modified in this edit object properties (hotkey 'q') window or by selecting the 'Instance' option and completing the form.
With the interface elements configured and the hierarchy managed (in the 'config' view), simulation now diverges in multiple orthogonal possible directions. Among the options for doing mixed-mode simulation are the Spectre environment through Analog Artist, Mentor Graphic's ADVance_MS through Analog Artist, and the Cadence AMS Simulation Environment through the Hierarchy Editor.
Using the MGC ADV_MS simulator is not covered in this tutorial at this time.
For simulating the Spectre environment, remember that just schematics and veriloga (and SpectreHDL) can be simulated with Spectre, but that verilogams and verilog along with any analog components (schematic, veriloga, etc) must be simulated with SpectreVerilog. Further note that in order to simulate VHDL in SpectreVerilog, the VHDL must be imported to verilog first (to the best of our knowledge). This process is not covered in this tutorial.
It is also important to note that because the Spectre simulator/viewer was developed to handle analog design data, AMS simulation is not always graceful. The amount of data generated is difficult to display in the analog waveform viewer. Probing internal nets of the behavioral modules is exceptionally cumbersome. Consequently, we recommend focusing AMS simulation attention on the AMS Environment (or ADV_MS) rather than Spectre. The AMS Environment essentially ports the simulation into the digital native compiled simulator (ncsim) environment, running the digital simulation and controls in the foreground, and encapsulating the analog simulation to run in the background in Spectre (under the control of ncsim). And we believe that the SimVision is better able to handle (copious amounts of) AMS simulation data, given its ability to handle massive amount of digital simulation data.
[The AMS Simulation Environment is only available from Cadence for HP and Sun operating systems at this time; Linux is not yet supported. Linux availability is anticipated at Ohio State in Autumn of 2004.]
Cadence provides some good documentation on using the AMS Simulation Environment:
The former is the AMS Environment User Guide, while the latter is the AMS Simulator User Guide. They are parallel documents in describing the AMS Simulator Environment, with the AMS Environment User Guide being more specific on how to navigate the Cadence windowing system to move a design from schematic to simulation and with the AMS Simulator User Guide being more specific on the command line commands and options. However, these two documents are in the IC Cadence package tree, and the simulator is actually in the LDV Cadence package tree. A problem occurs when the IC tree assumes that a certain version of the LDV tree is installed, such as the IC5.0 tree assuming that the LDV5.0 tree is installed, while only the LDV4.1 tree is actually installed. For this reason, we recommend cross-referencing/learning about the AMS Simulator and SimVision commands from the concise NC-Verilog Tutorial, starting with the Simulating the Design section:
The Quick-Start Tutorial section of the AMS Environment User Guide gives a good overview of how to take a schematic to AMS simulation. It instills a good sense of the flow to follow. However, the tutorial has all of its configurations already setup, so we will try to specify what configurations are necessary to take an outside design to simulation in the environment.
Simulating VHDL requires that the standard VHDL libraries be mapped into the cds.lib:
This softinclude command has already been included in the MOSIS NCSU Cadence Design Kit (CDK).
An 'hdl.var' file is not absolutely necessary in the work directory, however it will suppress warnings and prevent (some) random behavior. Put the following contents into an 'hdl.var' file in the working directory:
Please note that the WORK variable must be set to the project directory to help make commands like:
to map the 'WORK' directory correctly.
Any Spectre model files need to have a corresponding '.apt' file, which summarizes the model file's contents. Specifically, any 'model.scs' file would require a 'models.scs.apt' file in the same directory whose contents are of the format:
where 'ami06N,' 'ami06P,' ... 'tsmc35P' are model names from the 'models.scs' file. Such a file already exists for the MOSIS NCSU CDK's Spectre models.
Please be aware that not all modules in the basic library are supported. Specifically, the 'patch' modules (to connect busses with different names) do elaborate correctly. The 'ripper' module is seemingly provided for this function, although a verilog/veriloga module can easily be used as a pass-thru module:
With these configurations, the flow of the Quick-Start Tutorial can be applied to other projects. Fundamentally, once a 'config' view has been created and setup with the desired views, there are very few (sometimes difficult) steps necessary to move the design into the ncsim environment:
During the design preparation stage, any compiler or elaborator errors will be flagged. To debug the oblique error messages that Cadence delivers, try at the command line:
where NOLSTD is an example error message to be searched and ncvhdl_p, ncvlog, and ncelab are the tools flagging the error or warning. This approach may not help, as nchelp sometime only gives the same terse response as the compiler.
Once in the ncsim environment, it is important to understand that the desired signals to be probed must be specified before simulation. And there does not seem to be an easy methodology to reset the ncsim environment simulator; once it runs, it must be closed before re-running the simulation. For this reason, the commands used at the ncsim environment command line can be saved into a TCL script (which can be specified/input on the 'config' view window AMS -> Options -> Simulator page) and are automatically saved into a ncsim.key file either in the run directory or the working directory.
To set which signals are to be probed in the ncsim environment window manually, launch the Set Probe window (Set -> Probe). Next, launch the Design Navigator/Browser, and select the signals to be probed from any point in the hierarchy [Note that only analog nets, variables,and busses can be probed.] The selected signals automatically are transferred to the Set Probe window. Set the 'add to waveform display' box in the Set Probe window and select the 'OK' button. The waveform window will launch with the selected signals. The Set Probe window can continue to be used to add as many signals as desired to the waveform SimVision window.
Once the desired signals have been added to the SimVision window, run the simulation. The data can now be viewed, printed, and exported.
Good luck.
If you have any comments, suggestions, or corrections, please email
I.E. Group
IE logos by Ben McCrea.