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Just some tips about LVSing in Cadence...

Using the NCSU design kit... On the layout window's toolbar -> NCSU -> Modify LVS Rules, set all of the options to be checked (except "Ignore Body Terminal").

In the LVS window, by default set only Rewiring and Terminals option. Device Fixing and Cross Reference can lead to misleading results if you do not know what you are doing.

When reading the output file, concentrate first on unmatched nets and terminals. The netbad.out, mergenet.out, and termbad.out will be the most helpful sections in diagnosing which nets and terminals are miswired. Start with these first.

Ignore the audit.out until you get the netlists to match logically. Then you can go fix device sizes. Also, if LVS misinterprets which device is which, these errors will be dubious anyway.

If you get a huge number of errors by climbing on simple heirarchical step, you probably have a ground or supply miswiring.

If you get mergenet.out report in the layout only, you can search for the layout nets OR uncheck Rewiring in the LVS panel and rerun LVS. This will disallow net merging by LVS and tell you in the netbad.out of the schematic section which schematic net is not connected.

A hint about the message merged nets... it does not mean you have a short, but that LVS had to merge the nets together in order to maximally match schematic and layout. The missing connection is in the view in which the error appears, or may indicate an accidental short in the other view.

If you have run LVS and make no changes to the layout/extracted view and re-run LVS, uncheck the extracted button in the LVS window; the LVS run will go much faster. Likewise with the schematic button.

The rules file is almost always called divaLVS.rul and is located in the technology library for your design (until you modify the LVS rules, then the divaLVS.rul file will be copied to your project library).

by John Sheridan Fisher