This step lets Cadence take the layout view of the cells used in your schematic and place
them in an automatically generated layout. This layout will later be exported into Silicon Ensemble for automatic
routing of signals between the cells.
From the CIW window, select File -> Export -> PRFlatten.
Fill out the Library Name,Cell Name, and View Name settings. The dialog box should look
similar to below. Make sure "Generate Physical Hierarchy" is selected. When done, click "OK."
If created successfully, there should be a new cell view called autoLayout in your simple_fifo -> topview
hierarchy. If you double-click on it, you should have all the needed standard cell abstracts placed on the layout. The
abstract cells only contain the layers and routing information that Silicon Ensemble needs to perform place and route. Next,
this view will be exported for use in Silicon Ensemble.
From the CIW window, select File -> Export -> DEF.
Fill out the Library Name, Cell Name, View Name, and DEF File Name settings. The dialog box
should look similar to below. When done, click "OK."