You now have a routed design that can be re-imported back into Cadence and treated like a normal silicon layout.
Go to your cadence working directory and type icfb &.
After icfb finishes loading, go to the CIW and select File -> Import -> DEF. Fill in the library name and cell
name that you used to create your original schematic. For "View Name", type layout. Check the Ref. Library Names box and fill in the library name: OSU_diglibimport_ami06. Also make sure you enter the
file name for your routed .DEF design, including the directory it resides in. The form should look like this when properly filled out.
When done, select "OK". You may see some warnings in the CIW, but a new view should exist in your design called
"layout".
Open the "layout" view. You should see the abstract standard cells along with the wires created during the routing
session. It should look similar to this:
To properly turn the "abstract" cells into "layout" cells in the imported
layout view, go to the Library Manager and select Edit -> Rename Reference
Library.
You may need to go to the location of the layout file, as in
~/Cadence Directory/simple_fifo/topview/layout/
and delete the layout.cdb.cdslck file if it exists.
In Library: simple_fifo
From Library: OSU_diglibimport_ami06
To Library: OSU_diglib_ami06
Click OK.