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Automatic Place & Route with Silicon Ensemble

1. Download the LEF (Library Exchange Format) file found here: OSU_diglib_ami06_schematic.lef. This file tells Silicon Ensemble physical information about the standard cell library used by Cadence.
2. Create a work directory for Silicon Ensemble such as:
   
   mkdir ~/se
   
   
3. Change to this directory:
   
   cd ~/se
   
   
4. Start Silicon Ensemble:
   
   sedsm &
   
   
5. After starting, Silicon Ensemble should look like this:
   
   
   
   
6. Select File -> Import -> LEF, select the .LEF file (in our case, schematic_UT_LP_AMI06.lef) and click "OK".
   
   If it imports successfully, this message should appear in the interaction window:
   
   
   
   
7. Next, import the DEF file by selecting File -> Import -> DEF, select the .DEF file (in our case, simple_fifo_unrouted.def), and click "OK".
   
   If the interaction says that you have zero PROBLEM/ERROR messages, the design has been imported correctly.
8. Initialize Floorplan. Select Floorplan -> Initialize Floorplan. Select the "Flip Every Other Row" option, and change the IO To Core Distance to leave room for power and ground rings. Click "Calculate" and check to make sure the "Core row utilization" less than 100%. If it is not, change the "Core Area Parameters" to lower the percentage and click "Calculate" again. Choosing 75% for Core Row Utilization seems to work well for this very small design. The Initialize Floorplan menu should look similar to this:
   
   
   
   When you are happy with the results, click "OK."
   
   The floorplan that results may look like this:
   
   
   
   
9. Place IOs. Select Place -> IOs. Leave the defaults on and select "OK." This should randomly place pins around the edges of the design.
10. Place Cells. Select Place -> Cells. Leave the defaults on and select "OK." The standard cells should be placed on the design. If successful, the floorplan should look like this:
    
    
    
    
    
    
11. Place Filler Cells. Select Place -> Filler Cells -> Add Cells. For "Model", enter in FILL, and for Prefix, enter in any name such as "fill." For the Placement options, make sure only North and Flip South options are selected. Also, you can add vdd! and gnd! as Special Pins and Special Nets. If you do not, the power routing will work slightly differently, but you will receive less warning messages later on in the place-and-route process. The form should look like this:
    
    When done, click "OK". Filler cells will be added to provide uniformity across the circuit.
12. Route Power and Ground. Select Route -> Plan Power. When the Plan Power menu comes up, select Add Rings. Change the "Core Ring Width" to select the width of the power and ground rails. The window should look similar to this:
    
    
    
    When done, click "OK". You may close the Plan Power menu by selecting "Close". Power and ground rings should now encircle the cells. If there is not room for the rings, you may have to resize the floorplan.
13. Connect Rings. If you put the vdd! and gnd! information in the fill cell form, you can connect the rings using: Select Route -> Connect Ring. Leave the defaults and select "OK". You may not see any change, but this should not matter. If you did not add power and ground rail information to the fill cell form, skip this step.
14. Final Routing. Select Route -> WRoute. Make sure "Global and Final Route" is selected and click "OK". The final route may take a significant amount of time depending on how large the design is. The final route for the test design looks like this:
    
    
    
    If you added the vdd! and gnd! information to the fill cell form, you may get geometry violation errors at the interface between fill cells and regular cells. These are not really problems, and can be ignored, although it may make it harder to find real geometry violations. If you did not add this information, the power and ground routing will be done with minimum-sized wires, and will not connect consistently to the power and ground rings. There will be no geometry violation errors, though. This quirk is a function of the DEF import option in Silicon Ensemble requiring a modified LEF file.
    
    You can rerun some of these commands now to adjust the pin placement and routing. This is left as an exercise for the reader.
15. To export the finished design back into Cadence, select File -> Export -> DEF. Fill in the form and make sure that at least the below options are selected:
    
    
    
    You may now exit Silicon Ensemble.