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Place & Route Tutorial

1. Get needed Libraries
   OSU_digital_ami05.lef : Library Exchange Format of digital cell library.
   OSU_digital_ami05_gates.v : Verilog modules of digital cell library gates.
   miniUART_built.v : Verilog design netlist.
   
   
2. Start Silicon Ensemble. If you do not have Cadence version IC50 set up already, you need to source the Cadence startup information at the UNIX command line:
   
   source /opt/local/cadence/Startup.EE
   
   Then start Silicon Ensemble using the command:
   
   sedsm -m=500 &
   
   This starts Silicon Ensemble and allocates 500 MB of memory (good for very large designs).
   
   
3. Import LEF. Select File -> Import -> LEF, select the correct LEF file, and click "OK".
   
   
4. Import Verilog. Select File -> Import -> Verilog. Enter miniUART_built.v (your design) AND digital_lib_ami05_gates.v. Enter the Verilog Top Module (bidir in the example) to the form. The default options should already be correctly set up for vdd! and gnd! nets. Click "OK".
   
   
5. Initialize Floorplan. Select Floorplan -> Initialize Floorplan. Check the Flip Every Other Row and Abut Rows options. Change the IO To Core Distance to 20 microns (or higher) for each. You may need to change the Cell Density to 75%, which will make the design less dense, to allow room for routing. Then click "OK".
   
   
6. Place IO's and Cells. Select:
   
   Place -> IOs. Click "OK". This will place all the I/O pins.
   
   Place -> Cells. Click "OK". This will place all the standard cells specified in the design.
   
   Place -> Filler Cells -> Add.
   
   • Model: fill1
   • Prefix: fill1
   • Placement: ONLY North and Flip South checked.
   • Special Pins:
     Special Pin:
     • vdd!
     • gnd!
     
     Special Net:
     • vdd!
     • gnd!
     
     
   Click "OK" when finished. This will place filler cells between gaps in the placed standard cells, so that there is nwell and power and ground rail continuity across the layout.
   
   
7. Routing. These steps add power and ground rings, connect the power and ground rails to the rings, and routes all connections between the cells.
   
   First, select Route -> Plan Power and select Add Rings. Fill in the Core Ring Width to the desired width (3.00 microns for both, for example). Click "OK", then click "Close".
   
   Next, select Route -> Connect Ring and click "OK" to connect the power and ground rails to the rings.
   
   Finally, select Route -> WRoute, select Global and Final Route and Auto Search and Repair. Click "OK". Silicon Ensemble will try to do all wire routing in this stage. This may take a long time, depending on the complexity of the design, and the density of the wiring. There should not be any errors or geometry violations if the routing was successful. If there are any geometry violations, a large light-blue "X" will show up on the layout.
   
   
8. Export Design. This will export the design into a DEF (Design Exchange Format) file.
   
   Select File -> Export -> DEF. Fill in the name (miniUART.def)
   
   Select:
   • Cells
   • Nets
   • Special Nets
   • Vias
   • Groups
   • Modifications
   • Layout Modifications
   Click "OK". You may now exit Silicon Ensemble.
   
   

Import into Cadence

1. Create a new library (miniUART) attached to the NCSU_TechLib_ami06 library.
2. Import the Verilog netlist. The netlist that was used for place-and-route can be imported into Cadence as a schematic view.
   
   Select File -> Import -> Verilog.
   Enter:
   Target Library Name : miniUART
   Reference Libraries : OSU_digital_ami05
   Verilog Files To Import : miniUART_built.v
   Check Overwrite Existing Views if necessary.
   
   Click "OK" when finished.
   
   
3. Import Layout.
   
   Select File -> Import -> DEF.
   Enter:
   Library Name : miniUART
   Cell Name : miniUART
   View Name : layout
   Use Ref. Library Names : digital_lib_ami05_import
   DEF File Name : path/filename (as in: ~/flow_tutorial/se/miniUART.def)
   
   Make sure you open the new cellview and save it.
   
   
4. Finish Layout. To properly turn the "abstract" cells into "layout" cells in the imported layout view, go to the Library Manager and select Edit -> Rename Reference Library:
   
   Enter:
   In Library : miniUART
   From Library : digital_lib_ami05_import
   To Library : digital_lib_ami05
   
   Click "OK".
   
   If this is not successful, you may need to go to the location of the layout file, as in:
   
   ~/Cadence Directory/miniUART/miniUART/layout/
   
   and delete the layout.cdb.cdslck file, if it exists. Then, try this step again.