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Top Level Integration Methods

Project Hierarchy:

• top_level (not necessary for class projects)
  • finishing_cells (contains scribe lane, rev block, etc; not nec.)
  • asic_core_pads (required for class projects)
    • padframe (required for class projects)
    • asic_core (required for class projects)

Methodology:

• Copy the padframe cell but NO pads to your own project directory, then swap in the pads that you need into the layout and schematic. Be very CAREFUL not to move any structures in the padframe layout; any unintentional movement will cause the pads (and thus your design) to fail.
• Your project core should be called asic_core, which should include routing to the pad pins.
• The layout to be submitted to the foundry should be called asic_core_pads, which may ONLY, ONLY have asic_core & padframe in it, NO routing or other structures.
• The layout asic_core must be DRC'ed & LVS'ed, while the layouts padframe & asic_core_pads must (only) be LVS'ed.
• Once a vddpad and gndpad have been swapped into your padframe layout, please delete the VDD and GND pins from the padframe schematic.
• Once the padframe schematic with the proper pads has passed LVS, I recommend copying the padframe schematic as the asic_core_pads schematic; making a symbol for the asic_core schematic, which passed DRC & LVS and whose pins are in the same order and orientation as the pad frame pins; and of course inserting and wiring the asic_core symbol into the asic_core_pads schematic.