The Serial Peripheral Interface

Background
The Nautilus chip is a single chip solution for receiving a standard 4-20 mA analog communications protocol, converting the received analog to 16-bit digital words, and transmitting the digital words on a standard SPI (Serial Peripheral Interface) interface. The ADC (analog-to-digital converter) uses a second order Sigma-Delta A/D topology and is followed by a third order sinc filter. The sinc filter also includes the necessary control logic to interface with the on-chip SPI core. The SPI core transmits the 16-bit digital words across a standardized, fully configurable SPI serial interface as 16-bit/8-bit data. In addition, the SPI core can receive data for the ADC, such as filter coefficients.

The Nautilus chip was a research effort of the IEG (Information and Electronics Group) at The Ohio State University during the second quarter of 2000. The chip was fabricated by MOSIS during the third quarter of 2000 and will be extensively tested.

Introduction
This digital block of the mixed-signals ASIC chip was designed as a reusable core to aid in future projects of the IEG. The design was initially developed and tested in behavioral VHDL using Mentor Graphics Tools. This description was then ported to the behavioral VHDL subset supported by the Alliance Tools in order to use their free logic synthesis and automatic place-and-route tools. The layout generated was submitted to MOSIS for fabrication alongwith the other blocks that formed part of the Nautilus chip.

A Generic SPI Specification

The Nautilus SPI Core

A Generic SPI Specification
The SPI is essentially a three-wire serial bus for eight or sixteen bit data transfer applications. The three wires carry information between devices connected to the bus. Each device on the bus acts simultaneously as a transmitter and receiver. Two of the three lines transfer data (one line for each direction) and the third is a serial clock. Some devices may be only transmitters while others only receivers. Generally, a device that transmits usually possesses the capability to receive data also. An SPI display is an example of a receive-only device while EEPROM is a receive and transmit device.

The devices connected to the SPI bus may be classified as Master or Slave devices. A master device initiates an information transfer on the bus and generates clock and control signals. A slave device is controlled by the master through a slave select (chip enable) line and is active only when selected. Generally, a dedicated select line is required for each slave device. The same device can possess the functionality of a master and a slave but at any point of time, only one master can control the bus in a multi-master mode configuration. Any slave device that is not selected must release (make it high impedance) the slave output line.

The SPI bus employs a simple shift register data transfer scheme : Data is clocked out of and into the active devices in a first-in, first-out fashion. It is in this manner that SPI devices transmit and receive in full duplex mode.

All lines on the SPI bus are unidirectional: The signal on the clock line (SCLK) is generated by the master and is primarily used to synchronize data transfer. The master-out, slave-in (MOSI) line carries data from the master to the slave and the master-in, slave-out (MISO) line carries data from the slave to the master. Each slave device is selected by the master via individual select lines. Information on the SPI bus can be transferred at a rate of near zero bits per second to 1 M bits per second. Data transfer is usually performed in eight/sixteen bit blocks. All data transfer is synchronized by the serial clock (SCLK). One bit of data is transferred for each clock cycle. Four clock modes are defined for the SPI bus by the value of the clock polarity and the clock phase bits. The clock polarity determines the level of the clock idle state and the clock phase determines which clock edge places new data on the bus. Any hardware device capable of operation in more than one mode will have some method of selecting the value of these bits. This multi-mode capability combined with the simple shift-register architecture makes the SPI bus very versatile, and allows many non-serial devices to be used as SPI slaves.

The Nautilus SPI Core

The Nautilus SPI Core was designed to enhance the basic functionality of a generic SPI core for supporting different clock rates, communicating with several slaves and to enable extensive testing.

The Host Side configures the internal programmable registers for the SPI, provides the direction of data transfer, and the clock to drive the SPI. The Host Side also provides an asynchronous input to the SPI for latching data from a 16-bit data bus and accepts an asynchronous interrupt output from the SPI at the completion of data transfer.

The SPI Side is essentialy a three wire bus with the SPI clock, serial input and serial output lines corresponding to the MOSI and MISO lines of the generic SPI specification.

This core has been provided with a Divided Bus Mode to ease interface issues with 8-bit microcontrollers and enable operation on a multiple device network. In this mode, the lower byte lines of the data bus is used for 8 bit transfers while the higher byte lines are used for slave selection and control.

The internal structure of the SPI is composed of a Register unit, Clock unit, IRQ unit, Bus Divide unit, Input Latch unit, Test Unit, Receive Register, Transmit Register, and a  Control Unit.

The Register unit forms a set of four dual ported registers : Control Register, Status Register, Select Count Register and Data Buffer Register. This provides control and status inputs to the other units and accepts status outputs from the other units. Data may be transferred into/out of the registers in the 16-bit bus mode when the host selects a register through a 2-to-4 decoder block.

The SPI clock is generated from the Host Side input clock through a clock divider unit that can generate clocks at rates between 8 bits per second to 1 M bits per second, in any multiple of 8 in master mode operation. The phase, polarity and rate are configured according to the options set in the Control Register. In slave mode operation, the clock is sensed by the SPI. The transfer of a specific number of bits is also possible through options set in the Select Count Register.

The Bus Divide unit enables the Divided Bus Mode, the IRQ unit, when enabled,  interrupts the host on data transfer completion and the Input Latch unit is used for buffering data inputs from the Host Side. The Transmit Register is a parallel load shift register with serial output while the and Receive Register is a serial load shift register with parallel output.

The Test unit has been designed to enable the chip to perform self-verifcation tests. This unit implements a black-box testing scheme and has access to the Host Side interface and the Register unit.

The Control unit defines the interaction between the other units and is responsible for managing internal and external data bus transfers. Some of the operations performed by the Control unit include the determination of start of serial transfer, generation of status bits for parity, overrun, IRQ, etc.

Last updated: 12.45 ET Jan 07, 2001