Abstract:

Although sigma delta concepts have existed since the middle of the century , they have become more attractive only lately due to advances in VLSI technology.Using sigma delta converters , high resolution can be obtained for only low to medium signal bandwidths.

The theoretical basis and design techniques of incremental converters for obtaining optimum performance is presented. Matching of elements that enable using multi bit quantizers are also studied. A suitable architecture and signal processing techniques will also be discussed.

Abstract:

A 1.5V,12-bit,16 MSPS analog-to-digital converter was implemented in
0.25um 1P5M standard CMOS process with MIM capacitors. The converter
achieves a peak SNDR of 66.5dB with 5.12MSPS and that of 63.0dB with
16.384MSPS. The dynamic range is 68dB under both sampling rates. The
maximum INL of +-0.8LSB and DNL of +-0.5LSB were measured under 5.12MSPS.
while those of 16.384 MSPS decreased to +-3.1 and +-1.0LSB, respectively.
An embedded bandgap reference circuit that provides the conversion voltage
range is also presented with 1.5V supply voltage. The total power
consumption of this converter was 138mW under 16.384MSPS or 97mW under
5.12MSPS. The total area of this chip is 2.8X2.5mm. This chip was
implemented without calibration or trimming approaches.

Agenda:

Introduction to Project
Project Goals
Design Considerations
Design Challenges
Individual Progress
Comments/Questions