WCDMA/GSM/DECT Multi-Standard Architecture

Receiver ICs for certain standards using zero-IF architecture, such as GSM, DBS, WCDMA, DECT, WLAN are widely reported in the recent literature. It is observed that zero-IF architecture, which has been proven for dual-mode GSM handsets, is receiving considerable attention, compared to other architecture, for future single-chip multi-standard receivers.

The air interfaces of the target multi-standard receiver are listed in Table 1. Note that TDD WCDMA is discussed here. Based on our detailed analysis of receiver architectures and the three standards, a zero-IF multi-standard receiver architecture is proposed. Figure 2 depicts the proposed zero-IF radio architecture for a TDD UMTS (WCDMA/GSM) with DECT-supportive terminal. Because of the TDD operating mode the terminal does not require simultaneous transmission and reception, thus a TDD switch can be used at the front-end instead of a duplexer. For a FDD UMTS terminal, the TDD switch should be replaced by a duplexer for WCDMA while the TDD switch is still needed for GSM and DECT.

Table 1. Radio Specifications of WCDMA/DECT/GSM

Because of the different operating frequency bands, three sets of band filters and LNAs, which are basically narrow band components, are required to complete the band selection and low noise amplification. Several digital control signals from digital baseband processor control the power supply of the three LNAs so that only one required LNA is powered on and the other two are powered down. Two I/Q mixers are shared by all three standards because mixers are basically wideband components. In the proposed receiver, the baseband filter, variable gain amplifier (VGA) and A/D converter are all shared by the three standards. However, the baseband filter functions as a channel filter for WCDMA standard only. For DECT/GSM standards, it operates as an anti aliasing filter. The VGA's (variable gain amplifier) dynamic range is calculated to satisfy all the standards. The A/D converter is realized by a programmable delta-sigma modulator. The resolution and signal bandwidth of this A/D converter are controlled to satisfy the three standards. The decimation filter following the analog modulator performs channel filtering for the DECT/GSM standards. Using this architecture, the three standards signals are processed by the same receiver. Except for off-chip band filters and on-chip LNAs, all building blocks are shared.

Figure 2. Proposed WCDMA/GSM/DECT Multi-Standard Receiver

Another approach to design the baseband chain and A/D converter is presented, where digitally programmable analog filter and amplifiers are needed for channel selectivity thus achieving selectivity and amplification of all standards in the analog domain. All the standards share one fixed low resolution, 5 to 7 bit, A/D converter.

Front-end Circuit Design Issues

RF circuits

In the multi-standard receiver, narrow band tuned LNAs are required to save power and achieve high gain in current sub-micron CMOS technologies. Since the frequency operating bands for GSM, DECT and WCDMA cover from 1805MHz to 2025MHz, three separate LNAs will be needed, one for each standard. A TDD and band selection switch is placed after the antenna. This switch is a single-pole-four-throw switch. The four throws are respectively WCDMA, DECT and the GSMreceiver modes and for transmission. It is controlled by signals from the DSP controller chip, which is shown in Figure 3 as Standard-Switching Signal. This signal also controls the on-off status of the three LNAs so that only one LNA is turned on when the receiver is operating. Considering the trade-off between dynamic range and sensitivity, each LNA should have switchable high gain and low gain mode.

Figure 3. RF Multi-band Front-end: Band filters and LNAs

The I and Q mixers are shared by all standards. Though highly-linear passive mixers in CMOS are successful, the importance of having combined gain from the LNA and mixer, which should be sufficient to overcome flicker and thermal noise in the baseband stages, rules out lossy passive mixers in zero-IF receiver. The IIP3 of a CMOS cascode LNA is quite high, typically greater than --5dBm if noise and matching requirements are met. Thus, the linearity of the subsequent stages tends to be the limiting factor. In particular, the downconversion mixers must achieve high linearity and a reasonable noise figure.

Single balanced mixer exhibits less input noise than that of double-balanced topology. But the double-balanced topoly entails much less LO-IF feedthrough and suppresses the effect of additive noise in the LO input. CMOS mixers typically demand large LO swings so that the switching pairs do not remain on simultaneously for a considerable period of time. Increasing the width of the switching devices can lower the required swing, but at the cost of increasing their noise contribution and higher capacitance in the RF signal path. Thus, the choice of device dimensions and bias current plays a critical role in the performance.

The interface between the LNA and the mixer needs particular attention. In a heterodyne receiver, an external image-reject filter is ac-coupled to the LNA at its input and subsequently to the mixer at its output. These two interfaces are both 50-ohm matched. In zero-IF architecture the impedance level and the coupling method at the interface between the LNA and the mixer are flexible. However, at the LNA's output node, either an on-chip inductor or off-chip inductor is necessary to tune out the capacitance at the interface node. Otherwise, it is impossible to get high gain at GHz range. A low-Q on-chip spiral inductor is preferred here because it can realize a broadband LNA gain without external tuning component. To eliminate even-order distortion from the LNA, a high pass network including an ac-coupling capacitor between the LNA and mixer is an easy and effective solution.

Baseband Circuits

The design of the receiver baseband circuits becomes progressively more difficult as the RF section incorporates fewer external components and hence performs a less portion of the overall signal-processing task. Furthermore, noise-linearity-power trade-offs limit the amount of gain provided by the LNA and mixer circuits. After the signal is downconverted to the baseband, it must be filtered, amplified and digitized. At the interface node between the mixer and the first baseband stage, the signal is still quite small and the interferers may be quite large (e.g. 60dB above the signal level). Thus, both the noise and the nonlinearity of the first baseband building block are critical. Second, to avoid lowering the voltage gain of the mixer, it must exhibit a relatively high input impedance.

The baseband processing includes filtering and VGA. In this multi-standard receiver architecture the analog baseband filtering processing is designed to satisfy the channel filtering of the WCDMA standard. The channel filtering of the GSM and DECT standards are realized by A/D converter's decimation filter. There are two branches for I and Q channels. Figure 4 presents one possible architecture of the baseband processing. The input differential signals come from the output of the mixer. Anti-aliasing filter is used to filter out the noise and blockers outside of the sampling frequency of the A/D converter. The combination of two Filter sections has enough attenuation of the blockers for the WCDMA standard. VGA1 and VGA2 realize the VGA function such that enough dynamic range is achieved. The interleaving of filtering and VGA helps to meet the required IIP3 specification of the whole receiver.

Figure 4. Baseband Filter Architecture

The Synthesizer

In Zero-IF receivers, the local oscillator frequency is always set to the center frequency of the desired signal. For the multi-standard zero-IF receiver, the LO is also switched among the three frequency bands. Since the total frequency band of the receiver is from 1805MHz to 2025MHz, which is not too large for the tuning range of one single voltage-controlled oscillator (VCO), it can be implemented either by one VCO or several VCOs for high phase-noise performance. Considering the multiple operating bands and different channel bandwidths, the frequency synthesizer architecture needs to be a fractional PLL and an array of loop filters should be used to optimize the loop transfer function such that the optimized switching time, spurious response and phase noise can be obtained for each standard. If a single VCO is used, the phase noise performance of the VCO must be good through a wide range of offset frequency. One more easy method is to use multiple varactors to cover different RF bands. The phase noise performance requirement will be discussed in the following sections.

Figure 5. Local Oscillator Architecture

Radio System Analysis

In this section, the system requirement of the radio physical layer for the multi-standard receiver is described. This includes sensitivity, blocking characteristics and intermodulation characteristics. These test conditions given in the standard specification document are closely related to the receiver's specifications, such as: noise figure, IIP3, dynamic range and filtering processing. The three standards, WCDMA, GSM (DCS1800) and DECT are then analyzed one by one. In the end, the multi-standard receiver's specification is concluded.

Test Environment of System Specification

*Reference Sensitivity

The reference sensitivity is the minimum receiver input power measured at the antenna port at which the Bit Error Rate (BER) does not exceed a specific value. The noise and sensitivity specifications of WCDMA/GSM/DECT standards are shown in Table 1. The Noise Figure (NF) requirement of the receiver can be calculated by rearranging equation 1:

Note that for a WCDMA system, another factor, which is the processing gain (PG), should be included in the calculation. According to the WCDMA standard document, the sensitivity requirement is defined for the signal bit rate of 12.2kpbs while the chip rate is 3.84Mbps. Thus the processing gain, which is the ratio between the two rates, is 25dB. Because of the processing gain, the required NF is greatly relaxed.

*Blocking Requirement

The blocking characteristic is a measure of the receiver's ability to receive a wanted signal at its assigned channel frequency in the presence of an unwanted interferer on frequencies other than those of the spurious response or the adjacent channels, without this unwanted input signal causing a degradation of the performance of the receiver beyond a specified limit. Blocking requirement mainly affects the dynamic range and filtering of the receiver building blocks.

*Intermodulation Requirement

Third and higher order mixing of two interfering RF signals can produce an interfering signal in the band of the desired channel. Intermodulation response rejection is a measure of the capability of the receiver to receive a wanted signal on its assigned channel frequency in the presence of two or more interfering signals, which have a specific frequency relationship to the wanted signal. The intermodulation requirements for the three standards are shown in Table 2. The required IIP3 can be obtained using the information in Tables 1 and 2.

Table 2. WCDMA/GSM/DECT Intermodulation Requirement

WCDMA System Analysis

WCDMA sensitivity is specified as the minimum input power measured at the antenna at which the BER does not exceed 10^-3. For this BER, the received signal power level should be less than or equal to --117 dBm/3.84MHz. Also the signal is defined as having a data rate of 12.2kps and a spread chip rate of 3.84Mbps. So the processing gain (Gp) of the system can be calculated as:

Based on the 3GPP Radio Access Networks Technical Specification Group, the Eb/N0 required for the baseband receiver for a BER of 10^-3 is 5.2dB. Including a 2dB implementation margin, it would be 7.2dB. Then the receiver NF can be calculated using equation 3 with processing gain:

Stringent dynamic range specifications place large signal handling requirement on the WCDMA receiver mode. In WCDMA, the BER cannot exceed 10^-3 when an average input power of -25dBm/3.84MHz is applied at the antenna. Given a peak-to-average power ratio of about 7dB for the WCDMA signal, the peak power at the antenna could approach -18dBm/3.84MHz. As the level of the received signal approaches the receiver's -1dB compression power, the distortion increases and thus reducing the Eb/N0 and increasing the BER. A low-gain mode of LNA is used to relax the requirement of the following building blocks, especially the receiver AGC range. When the LNA is in low-gain mode, the input signal level is less amplified and the linearity and current consumption requirement of the VGA can be reduced.

In WCDMA the adjacent channel selectivity (ACS) is defined as a measure of the receiver's ability to receive a WCDMA signal at the assigned channel frequency, in the presence of an adjacent modulated channel signal at 5MHz offset from the center frequency of the assigned channel. ACS is the ratio of the receive filter attenuation at the assigned channel frequency to the receiver filter attenuation at the adjacent channels. The power of the wanted signal is -93dBm/3.84MHz while the modulated interferer is -52dBm/3.84MHz. Together with the blocking characteristics test shown in Table 3, two specifications need to be derived. One is the selectivity of the filtering process and the other is the LO's phase noise performance.

Table 3. WCDMA Blocking Requirement

First let us calculate the LO phase noise requirement. At the mixer output, the blocker signal reciprocal mixing with the LO phase noise creates an interferer within the desired signal band. If the phase noise is assumed to be flat across the band of interest, the power of this interferer is:

where PI PI is the reciprocal mixing product, PB PB is the corresponding blocker power at the mixer output, delta-f _f is the offset frequency, BW BW is the bandwidth of the signal and PN is PN the phase noise spectrum density. In the WCDMA mode, the 5MHz adjacent channel signal power is --52-(-93)=41dB higher than the desired signal, then the difference between PI and the desired signal is 41dB + [PN(delta-f)+1-log(BW)]. To keep this interference 15dB lower than the signal, then the phase noise requirement is:

Here we have BW BW is 3.84MHz, then the phase noise at 5MHz offset should be less than -125dBc/Hz. To make it more general, the phase noise requirement can be expressed as:

where SIR is the expected signal to the reciprocal mixing interferer ratio. Using the same equation, we can get the phase noise at 10MHz and 15MHz offsets according to the blocking characteristics shown in Table 3. In the blocking characteristics test, the desired signal level is -107dBm/3.84MHz. So for the phase noise at 10MHz offset:

and for the phase noise at 15MHz offset:

3GPP ACS test already gives the filter attenuation as 33dB at 5MHz offset. The baseband filtering attenuation of the receiver at 10MHz and 15MHz offset can be easily calculated as:

According to the intermodulation characteristics test environment, two interfering signals at 10MHz and 20MHz offset frequency are both at -46dBm power level. The input signal is at -107dBm and the receiver's BER should be kept lower than 10^-3. As we mentioned earlier, this BER corresponds to 7.2dB C/I, i.e. carrier-to-interference ratio, at the output of the receiver. Though it is an intermodulation test, it also includes the effects of noise in the receiver channel. Therefore, the distortion (intermodulation) components plus the white noise in the receiver together should satisfy the C/I requirement. Actually the desired signal level is 3dB above the sensitive requirement. So what the receiver needs to do is to manage the ultimate intermodulation product as low as the white noise power level. Then the receiver's C/(I+N), where N stands for noise, is just enough for BER requirement considering that the white noise is uncorrelated with the intermodulation components. According to the noise figure calculation, we know that the maximum receiver input referred noise floor is at --117dBm -- 7.2dB + 25dB = -99.8dBm. So we also want all the intermodulation components from the receiver to remain less than -99.8dBm when referred to the receiver input. If the two intermodulating adjacent channels are applied to the receiver at -46dBm then we know that the IM3 component must be:

The input referred IP3 can be then calculated as:

DCS1800 System Analysis

The sensitivity requirement for DCS1800 is -100dBm with the required C/I of 9dB at the receiver output so that the BER can be kept lower than 10^-3. This reflects a noise figure of 11.98dB.

The blocking test for DCS1800 is performed by applying a GMSK modulated desired signal 3dB above the required receiver reference sensitivity. Then a single unmodulated tone is applied to the receiver at discrete increments of 200KHz from the desired signal with a magnitude shown in Table 4.

Table 4. GSM(DCS1800) Blocking Requirement

In our proposed receiver, the analog filter has no attenuation of the blockers. Thus, a very high-resolution A/D converter is needed. The blocking characteristics here mainly influence the specification of the ADC. This will be discussed in the following sections. The phase noise specification of the LO can also be derived using equation 6.

According to the definition of intermodulation test in DCS1800, the receiver must maintain 9dB C/I at the output of the receiver with the adjacent channel power of -49dBm. The maximum receiver input referred noise floor is at -109dBm and the desired signal is at -97dBm. The IM3 component must be:

Therefore, the input referred IP3 is,

Which gives us a -19dBm input referred IP3 or better required of the receiver to be compliant with the DCS1800 standard.

DECT System Analysis

The sensitivity for DECT is -83dBm with required C/I of 10.3dB at the receiver output so that the BER can be kept lower than 10^-3_3. So the noise figure of DECT is:

DECT has considerably easier blocking requirements as compared to DCS1800. A set of test conditions is given for both inband and out-of-band blocking signals. For the inband blocking, the receiver must maintain 10^-30_3 BER when a -73dBm desired signal is applied to the receiver and a single blocker is applied to the input of the receiver. The blocker is a GMSK modulated signal of power levels given in Table 5. The blocking requirements include an -83dBm Co-Channel blocker (The Co-Channel blocker is an interferring signal applied in the same band as the desired signal). All of the inband blocking tests are repeated for each of the adjacent channels. For the out-of-band blocking, a desired -73dBm input signal is applied to the receiver in channel 4, which is located at 4 times the channel spacing away from the desired signal. Then a single unmodulated blocker is applied in each of the bands with the signal strength indicated in Table 5. Same as the situation for DCS1800, the analog baseband filter though has some attenuation on the blockers, is not a channel filter. So the analog filter's attenuation characteristic is not important for the DECT mode. The blocking test will influence the ADC specification. This will be fully analyzed in the following sections. The phase noise requirement for DECT LO can be calculated, using equation 6.

Table 5. DECT Blocking Requirement

Note that the phase noise requirement is pretty relaxed compared with that of DCS1800. Similar to WCDMA and DCS1800, the DECT standard outlines a set of conditions to test the intermodulation performance of the receiver. A desired signal is at -80dBm. Two adjacent channel signals are applied with a -46dBm input power. Using the same procedure to calculate the IIP3, we have an IIP3 for DECT of:

Baseband Filter and ADC dynamic range

To follow the receiver chain specification, in full details, is a complex task. Based on the proposed multi-standard WCDMA/GSM/DECT receiver architecture, the baseband filter order and ADC dynamic range can be determined first. In the receiver, the baseband filter operates as a channel filter for WCDMA standard while for DCS1800/DECT standards, it is an anti-aliasing filter. Because the anti-aliasing filter's specification is rather easy to realize, the filter specification is mainly determined by WCDMA blockers requirement and ADC's dynamic range. Actually the order of the filter and ADC's dynamic range can be traded with each other. A higher order filter leads to a low-resolution ADC while a lower order filter must be combined with a high-resolution (dynamic range) ADC to cope with the signal and the blockers.

First, the filter characteristic can be easily derived based on the WCDMA system analysis in the previous section. This is shown in Table 6 together with the ideal 6-th order and 5-th order butterworth filter specifications. In the table, the offset frequency means the offset from the center of the desired signal. It is easy to conclude that a 6-th order filter is required for the baseband filter.

Table 6. Baseband Filter Specification

Actually the baseband filter has some attenuation for the DCS1800 and DECT's blockers, though the attenuation is not adequate. However here we do not consider the small amount of attenuation from the filter in DCS1800 and DECT operation because we assume that the baseband filter is in low power mode in DCS1800/DECTmodes. Under the low power mode the filtering characteristic is fairly relaxed and thus we cannot expect to have sharp attenuation of the blockers. Then the dynamic range of the ADC for DCS1800 and DECT standards can be calculated only based on the blocker test specifications. For DCS1800 the signal is at the reference level -97dBm together with the highest blocker, which is -26dBm at 3MHz. If we set the ADC's quantization noise to be 15dB lower than the desired signal, the ADC's dynamic range is:

For the DECT standard, the signal power is -80dBm and the blocker level is -33dBm at 5.184MHz and 6.192MHz. Still we set the ADC's quantization noise be 15dB lower than the desired signal, the ADC's dynamic range for DECT is:

In WCDMA ACS test, the signal power is -93dBm while the adjacent channel interferer is at -52dBm. Considering the channel filter attenuation on the adjacent channel to be 33dB, the adjacent channel interferer is still 8dB higher than the signal. Assume that the quantization noise in this mode is 20dB lower than the thermal noise, the ADC's dynamic range for WCDMA can be estimated as:

So the baseband filter and ADC's specification are set. The low-pass filter in the receiver is set to 6-th order and the ADC's dynamic range is 14bit, 11bit and 6bit for DCS1800, DECT and WCDMA respectively.

Up to now, we can summarize the system specifications for the three standards as shown in Table 7.

Table 7. WCDMA/DCS1800/DECT System Specification

Noise Figure, Gain and IIP3 Distribution

A TDD switch and a band-select filter are the two only off-chip components needed. The insertion loss of these components is set by checking the available components on the market. In our system, the total attenuation of these two components is set to be 4dB. Then the gain and noise figure of LNA and mixer are to be determined. Because we cannot afford a high noise figure deterioration from a passive Balun in the front-end, the three LNAs have a single ended input interface. The input must be matched to a standard 50-ohm load. The gain and noise figure specifications were determined, and based on state-of-the art published RF CMOS circuits performance. The results are listed in Table 8.

Note that in the table, only high-gain values for LNAs are shown. These values are used when the received signal power is low. When the received signal at the antenna is high, the low-gain mode of LNAs is used, which is set to be 0dB. Though the gain is 0dB, it can not just pass through the signal from LNA input directly to the mixer since the LNAs' another important function is to provide enough reverse isolation to alleviate DC offset problem.

Table 8. Building Blocks Specification Distribution

To adjust the signal level at an appropriate level when it hits the input port of the A/D converter, a variable gain amplifier(VGA) is required in the AGC loop. The dynamic range of the VGA is calculated by investigating the large signal and small-signal operation. First, let us calculate the dynamic range for the WCDMA mode. When the signal is at the sensitivity level, which is -110dBm/3.84MHz or -93dBV, the whole receiver chain need offer 0dBV-(-93dBV)=93dB gain. Subtracting the gains of band-select filter (-2dB), TDD switch (-2dB), LNA(18dB) and mixer(8dB) in the receiver chain, the maximum VGA gain is 71dB. The maximum input power is -18dBm/3.84MHz or -33dBV, as pointed out earlier. At this condition, the LNA is set at the low-gain mode, which is 0dB. Thus the minimum gain from VGA is 33+2+2-0-8=26dB. So the VGA gain range is 26dB to 71dB, for a total of 45dB dynamic range. For DECT and DCS1800, the required dynamic range of the VGA is smaller than that of WCDMA. So the VGA is set based on the WCDMA standard.

The IIP3 requirement for the three standards is about -19dBm as calculated in the previous section. However in the physical implementation of the handset, the amount of transmitter leakage into the receiver front-end desensitizes the LNAs if its linearity is insufficient. To prevent this desensitization, expressed in equation 7, the LNAs IIP3 or input P1dB must be increased above those requirements set by the intermodulation test. Here we set IIP3 at -10dBm. According to equation 2.15, we evenly distribute the IIP3 specifications to mixer and analog low-pass filter. The result is that the IIP3 of the mixer is 8dBm and the IIP3 of the analog low-pass filter is 16dBm.

Delta-sigma Modulators and Multi-Standard Receivers

The delta-sigma modulator ADC constitutes the major part of the proposed multi-standard receiver. As mentioned in the previous part, only WCDMA channel filtering is realized in the analog baseband processing. The filtering of the baseband circuits has almost no attenuation on the blockers of GSM and DECT. Thus for GSM and DECT standards, the ADC needs much higher dynamic range (resolution) compared with the WCDMA standard. A high performance programmable delta-sigma modulator ADC provides a good solution for meeting these requirements.

Conventional Nyquist architectures are often difficult to implement very high dynamic range converters in fine-line very large scale integration technology. These difficulties arise because conventional methods need precise analog components in their filters and conversion circuits and because their circuits can be very vulnerable to noise and interference. The virtue of conventional methods is their use of a low sampling frequency, usually the Nyquist rate of the signal. Oversampling converters can use simple and relatively high-tolerance analog components to achieve high resolution, but they require fast and complex digital signal processing stages. These converters modulate the analog signal into a simple code, usually single-bit words, at a frequency much higher than the Nyquist rate. Thus the design of the modulator trades resolution in time for resolution in amplitude in such a way that imprecise analog circuits can be tolerated.

Oversampling delta-sigma modulators have been very successfully used in A/D conversion applications over the last two decades. Although the emphasis has been usually on low-speed, high-resolution applications, high-speed and high-resolution converters using oversampling delta-sigma Modulators have recently been reported. Basically, a delta-sigma Modulator exchanges resolution with speed. This inherent characteristic depicted in Figure 6 is suited for multi-standard wireless receivers because by choosing different bandwidths and different sampling speeds, the same A/D converter exhibits different dynamic range and resolution. In the proposed multi-standard receiver, the A/D converter needs to perform as a 14bit-100KHz converter for DCS1800, an 11bit-700KHz converter for DECT and a 6bit-2.5MHz converter for WCDMA.

Figure 6. Inherent Characteristic of delta-sigma Modulator A/D Converter

Summary

A WCDMA/GSM/DECT multi-standard receiver is analyzed in a top-down manner in this chapter. First the multi-standard receiver architecture is presented. Design issues in the front-end, the base-band and the frequency synthesizer are discussed. The receiver specifications are then derived from the system requirements. Combined with the architecture, these specifications are distributed to the building blocks such that the shared hardware satisfies the requirement of all standards. Though we discuss the multi-standard receiver for WCDMA, GSM and DECT systems, the analysis method and the receiver architecture can be easily adapted to other multi-standard applications.

*This is chapter 3 of “Multi-Standard CMOS Wireless Receivers: Analysis and Design,?published Kluwer Academic Publishers. It is reprinted here by an arrangement with the authors and publisher. For more information on this, and other Kluwer analog texts, go to www.kluweronline.com

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