ENTITY cntrtb IS
END cntrtb;

ARCHITECTURE one OF cntrtb IS
    SIGNAL sclk : BIT;
    SIGNAL ST_STOP,s1,s2 : BIT;
    SIGNAL alarm : BIT;
    
    COMPONENT cntrl
    PORT(ST_STOP : IN BIT;
      sclk : IN BIT;
      s1 : IN BIT;
      s2 : IN BIT;
      alarm : OUT BIT);
    END COMPONENT;
    
    FOR ALL : cntrl USE ENTITY work.cntrl(one);
    
BEGIN   
  --instantiate timer
  c0: cntrl PORT MAP(ST_STOP,sclk,s1,s2,alarm);
  --set up the clock signal with 100ns cycle
  sclk <= not sclk AFTER 50 ns;
  
  --process to control the timer
  PROCESS
  BEGIN
    -- set initial values for inputs
    s1 <= '1'; s2 <= '1'; ST_STOP <= '1';
    -- start tests by setting digit 1
    -- first test are to count up and set the counter
    s1 <= '0';
    wait for 1500 ns;
    s1 <= '1';
    s2 <= '0';
    wait for 1500 ns;
    s2 <= '1';
    wait for 500 ns;
    -- now run it
    ST_STOP<='0';
    wait;
  END PROCESS;
  
END one;