-- SYSTEM CONTROLLER
ENTITY cntrl IS
    PORT(ST_STOP : IN BIT;
      sclk : IN BIT;
      s1 : IN BIT;
      s2 : IN BIT;
      alarm : OUT BIT);
END cntrl;
  
ARCHITECTURE one OF cntrl IS
--internal signals
   SIGNAL cup,cdn : BIT;
	SIGNAL at0_0,at9_0,at0_1,at9_1 : BIT;
	SIGNAL cnt_0,cnt_1 : BIT_VECTOR(3 downto 0);
	SIGNAL iclk1,iclk2 : BIT;
	SIGNAL end1,end2 : BIT;
	SIGNAL min_clk_en : BIT;
	TYPE state_type IS (idle,set_d1,set_d2,run,s_alrm,stop);
	SIGNAL state,next_state : state_type;
	
	COMPONENT dig1
	   PORT (clk : IN BIT;
				cup,cdn : IN BIT;
				at0,at9 : OUT BIT;
				cnt : OUT BIT_VECTOR(3 downto 0));
	END COMPONENT;
	--FOR ALL : dig1 USE ENTITY work.dig(one);
	
	BEGIN
	  --wire in component
	  c0: dig1 PORT MAP (iclk1,cup,cdn,at0_0,at9_0,cnt_0);
	  c1: dig1 PORT MAP (iclk2,cup,cdn,at0_1,at9_1,cnt_1);
	
	  --F/Fs
	  PROCESS
	  BEGIN
	     WAIT UNTIL sclk='1' and sclk'event;
		  state <= next_state;
	  END PROCESS;
	  
	  --next state
	  PROCESS(state,sclk)
	  BEGIN
	     CASE state IS
		    WHEN idle => IF (s1='1' and s2='1' and st_stop='1')
			               THEN next_state <= idle; cup<='0'; cdn <= '0';
			                    min_clk_en<='0'; end1<='0';end2<='0';
							  ELSIF (s1='0')
							   THEN next_state <= set_d1;
							  ELSIF (s2='0')
							   THEN next_state <= set_d2;
							  ELSIF (st_stop='0')
							   THEN next_state <= run;
							  END IF;
			 WHEN set_d1 => IF (s1='1') THEN next_state <= idle;
			                 ELSE cup<='1'; end1 <= '1';
			                END IF;
			 WHEN set_d2 => IF (s2='1') THEN next_state <= idle;
			                 ELSE cup<='1'; end2 <= '1';
			                END IF;
			 WHEN run => IF (st_stop='1') THEN next_state<=idle;
			             ELSE 
			               cdn<='1'; end1<='1'; end2<='0';
			               IF (cnt_0="0000" and cnt_1/="0000")
			                 THEN end2<='1';
			               END IF;
			               IF (cnt_0="0000" and cnt_1="0000")
			                 THEN next_state <= s_alrm;
			               END IF;
			             END IF;
			 WHEN s_alrm => alarm<='1';
			                end1<='0';end2<='0';
			                 next_state<= stop;
			                 
			 WHEN stop => next_state <= idle;
		  END CASE;
	 END PROCESS;
	 
	 --Output and other logic
	 --enabling the internal clock
	 iclk1 <= sclk and end1;
	 iclk2 <= sclk and end2;
	 
  END ARCHITECTURE;