ENTITY dig IS
    Port (clk : IN BIT;
          cup,cdn : IN BIT;
          at0,at9 : OUT BIT;
          cnt : OUT BIT_VECTOR(3 DOWNTO 0));
END dig; 

ARCHITECTURE one OF dig IS
    SIGNAL icnt, inext_cnt : BIT_VECTOR(3 DOWNTO 0);
    SIGNAL incr_icnt : BIT_VECTOR(3 downto 0);
    SIGNAL incr_carry : BIT_VECTOR(4 DOWNTO 0) := "00001";
    SIGNAL idec_icnt : BIT_VECTOR(3 downto 0);
    SIGNAL idec_bor : BIT_VECTOR(4 DOWNTO 0) := "00001";
BEGIN
    PROCESS
    BEGIN
       WAIT UNTIL clk='1' and clk'event;
       icnt <= inext_cnt;
   END PROCESS;
   
   --NEXT state generation
   --CODE FOR INCREMENTER
   incr_icnt <= icnt xor incr_carry(3 DOWNTO 0);
   incr_carry(4 DOWNTO 1) <= incr_carry(3 DOWNTO 0) and icnt;
   --CODE FOR DECREMENTER
   idec_icnt <= icnt xor idec_bor(3 downto 0);
   idec_bor(4 DOWNTO 1) <= idec_bor(3 DOWNTO 0) and NOT icnt;
   PROCESS (cup,cdn,incr_icnt,idec_icnt)
   BEGIN
      IF (cup = '1' and cdn = '0' and incr_icnt = "1010")
       THEN inext_cnt <= "0000";
      ELSIF (cup = '1' and cdn = '0') 
       THEN inext_cnt <= incr_icnt;
      ELSIF (cup = '0' and cdn = '1' and idec_icnt = "1111")
       THEN inext_cnt <= "1001";
      ELSIF (cup = '0' and cdn = '1')
       THEN inext_cnt <= idec_icnt;
      END IF; 
   END PROCESS; 
   
   --Output process
   PROCESS(icnt)
   BEGIN
       IF icnt = "0000" THEN at0 <= '1'; ELSE at0 <= '0'; END IF;
       IF icnt = "1001" THEN at9 <= '1'; ELSE at9 <= '0'; END IF;
       cnt <= icnt;
   END PROCESS;
END one;