Hardware Description Languages
SPRING '08
Lectures (WI 2009)
M1: Lecture 1 - Course Introduction - ee762/LectWI09/L1 - Course Intro.ppt
W1: Lecture 2 - VHDL Introduction - ee762/LectWI09/L2-VHDL Introduction.doc
HW 1 - Introduction to Modelsim ee762/HW/HW 1.doc
F1: Lecture 3 - Data Paths - Lect 3 - Data Paths 1.ppt
M2: Project Step 1 - Lect 3 - Project Step 1.ppt
W2: Lecture 4 - Data Paths 2 - Lect 4 - Data Paths 2.ppt
F2: Project Step 2 - Lect 5 - Project Step 2.ppt
M3: Holiday
W3: Lecture 6 - Lect 6 - Language Overview I.ppt
Project Step 3 - Lect 7 - Project Step 3.ppt
F3: Continue Lecture 6
M4: Project Step 4 - Lect 9 - Project Step 4.ppt
Lecture 7 - Lect 7 - Language Overview II.ppt
W4: Continue with Lect 7 BUT ITS' A SNOW DAY!!!!!!!!!!
F4: Continue with Lect 7
M5: Lecture 8 - Lect 8 - Language Overview III.ppt Proj 4 due.
Project Step 5 Lect 11 - Project Step 5.ppt
W5: Finish Lect 8 - Language Overview III
Lecture 10 - Lect 10 - Attributes.ppt
F5: Exam Review
M6: MIDTERM
W6: Project Step 6 - Lect 15 - Project Step 6.ppt and review of project steps 1 through 5
Timing and Currency - Lect 12 - Timing & Concurrency I.ppt
F6: Continue with Timing and Concurrency
M7: Finish Lect 12
Timing and Concurrency II - Lect 15 - Timing & Concurrency II.ppt
W7: Resolved Signals - Lect 17 - Resolved Signals.ppt
Project Step 7 - Registers - Lect 18 - Project Step 7.ppt
F7: Timing and Concurrency III - WI09/Lect 16 - Timing & Concurrency III.ppt
M8: A complete datapath - Project Step 8 - Lect 20 - Project Step 8.ppt
W8: NO CLASS - On Travel
F8: Project Step 9 - A successive approximation A to D Lect 23 - Project Step 9.ppt
State Machine Descriptions - Lect 22 -State Machine Design.ppt
M9: Go over new material in Lect 22 and update on PS 9
Complete material in Timing and Concurrency III
W9: IEEE Floating Point Lect 24 -IEEE Floating Point Units.ppt
F9: Project Step 10 - Floating Point Adder Lect 25 - Project Step 10.ppt
Extra Credit Project Step Announced
M10: Lect 26 -IEEE Floating Point Adder Arch.ppt
W10: Lect 27 - Verilog Intro.ppt
F10: FINAL
Package STD1164_LOGIC std_1164.vhd
Assignments for WI 09 : WI09 Assignment Table.doc
HW1: Due Monday Jan 12: WI09/HW 1.doc
PS1: Due Friday Jan 16: PS1.doc pr_step1.vhdl
PS2: Due Wednesday Jan 21: PS2.doc pr_step2.vhdl
PS3: Due Monday Jan 26: PS3.doc pr_step3.vhdl ps3_list.do ps3_wave.do
PS4: Due Monday Feb 2 PS4.doc pr_step4.vhdl p4_list.do p4_wave.do
PS5: Due Friday Feb 6 PS5.doc pr_step5.vhdl p5_list.do p5_wave.do
PS6: Due Monday Feb 16: PS6.doc pr_step6.vhdl ps6_list.do ps6_wave.do
PS7: Due Monday FeB 23: PS7.doc pr_step7.vhdl ps7_list.do ps7_wave.do
PS8: Due Monday Mar 2: PS8.doc pr_step8.vhdl ps8_list.do ps8_wave.do
PS9: Due Monday Mar 9: PSsar.doc sar_tb.vhdl pssar_list.do pssar_wave.do
PS10: Due Monday Mar 16 - PS10.doc: fpm_your_model.vhdl fpmtb.vhdl fpm_list.do fpm_wave.do
Test Vectors fpmvectors LIST FILE error corrected
Path to library assign /rcc4/homes/degroat/ee762_assign
EXTRA CREDIT: pr_step_excr.vhdl excr_list.do excr_wave.do Lect 23 - Project Step Extra Credit.ppt
and start with your code and package from step 8
From previous offerings of the course for reference
Note that all links may not be active
Lectures (2007)
M1 Lecture 1 - Course introduction - ee762\Lectures\L1 - Course Intro.pdf
W1 Lecture 2 - Introduce HW1 - ee762\Lectures\HW 1.pdf
F1 Lecture 3 - VHDL Introduction - ee762\Lectures\L2-VHDL Introduction.pdf
M2 Lecture 4 - Datapaths - ee762\Lectures\Lect 3 - Data Paths 1.pdf and Project Step 1 - ee762\Lectures\Lect 3 - Project Step 1.pdf
W2 Lecture 5 - Processor Datapaths - ee762\Lectures\Lect 4 - Data Paths 2.pdf
F2 Lecture 6 - Project Step 2 - ee762\LecutresPwrPt\Lect 5 - Project Step 2.ppt
- Language Overview I - ee762\LecutresPwrPt\Lect 6 - Language Overview I.ppt
M3 - Finish Language Overview I
W3 - Project Step 3 - ee762\LecutresPwrPt\Lect 7 - Project Step 3.ppt
Lecture 7 - Language Overview II - ee762\LecutresPwrPt\Lect 7 - Language Overview II.ppt
F3 - Finish Language Overview II
M4 - Lecture 9 - Language Overview III - ee762\Lectures\Lect 8 - Language Overview III.ppt
Project Step 4 - ee762\Lectures\Lect 9 - Project Step 4.ppt
W4 - Finish Language Overview III
Lecture 10 - Attributes and Package Standard - ee762\Lectures\Lect 10 - Attributes.ppt
F4 - Lecture 11 - Project Step 5 - ee762\Lectures\Lect 11 - Project Step 5.ppt
M5 - Lecture 12 - Timing and Concurrency I - ee762\Lectures\Lect 12 - Timing & Concurrency I.ppt
W5 - Lecture 15 - ee762\Lectures\Lect 15 - Timing & Concurrency II.ppt
Project Step 6 - ee762\Lectures\Lect 15 - Project Step 6.ppt
F5 - Exam Review and go over solution to Project Steps 1 through 4
M6 - Midterm
W6 - Timing and Concurrency II
F6 - Lecture 17 - ee762\Lectures\Lect 17 - Resolved Signals.ppt
Project Step 7 - ee762\Lectures\Lect 18 - Project Step 7.ppt
M7 - Lecture 17 - continued
W7 - T'was a snow day but this quarter Lecture 20 - Project Step 8 - The complete datapath -
ee762\Lectures\Lect 20 - Project Step 8.ppt
F7 - Timing & Concurrency III
M8 - Timing & Concurrency III and Resolved Signals- ee762/Lectures/Lect 16 - Timing & Concurrency III.pdf
W8 - Lecture 22 - State Machine Design - ee762/Lectures/Lect 22 -State Machine Design.ppt
Project Step 9 - A sequential machine - ee762/Lectures/Lect 23 - Project Step 9.ppt
F8 - Finish State Machines and Review Exam 1
M9 -Lecture 23 - IEEE Floating Point p1 Units ee762/Lectures/Lect 24 -IEEE Floating Point Units.ppt
Extra Credit Project Steps - ee762\Lectures\Lect 23 - Project Step Extra Credit.pdf
W9 -Lecture 24 - IEEE Floating Point Units cont
Lecture 25 - Project Step 10 - Floating Point Multiplier - ee762/Lectures/Lect 25 - Project Step 10.ppt
F9 - IEEE Floating Point
M10 - HOLIDAY
W10 - finish Floating Point - Lecture 27 - IEEE FP Adder - ee762/Lectures/Lect 25 -IEEE Floating Point Adder Arch.ppt
F10 - Verilog - ee762/Lectures/Lect 27 - Verilog Intro.ppt
Assignments (SP 2008)
Homework 1 - Due Monday March 31 - ee762\Lectures\HW 1.pdf
Project Step 1 - Due Friday April 4 - ee762\PS1.pdf CODE FILE: ee762\pr_step1.vhdl
Project Step 2 - Due Wednesday April 9 - ee762\PS2.pdf CODE FILE: ee762\pr_step2.vhdl
Project Step 3 - Due Monday April 14 - ee762\PS3.pdf CODE FILE: ee762\pr_step3.vhdl .do FILES: ee762\ps3_list.do ee762\ps3_wave.do
Note that .do files for Step 3 have been updated as of April 9th,2008
Project Step 4 - Due Friday April 18 - ee762\PS4.pdf .do FILES: ee762\ps4_list.do ee762\ps4_wave.do
CODE FILE: ee762\pr_step4.vhdl
Project Step 5 - Due Wednesday April 23 - ee762\PS5.pdf CODE FILE: ee762\pr_step5.vhdl
.do files ee762\ps5_list.do ee762\ps5_wave.do
Project Step 6 - Due Wednesday Monday 13 - ee762\PS6.pdf CODE FILE: ee762\pr_step6.vhdl
.do files ee762\ps6_list.do ee762\ps6_wave.do
Project Step 7 - Due Wednesday May 7 - ee762\PS7.pdf CODE FILE: ee762\pr_step7.vhdl
.do files ee762\ps7_wave.do ee762\ps7_list.do
Project Step 8 - Due Wednesday February 28 - ee762\PS8.pdf . CODE FILE: ee762\pr_step8.vhdl
.do files ee762\ps8_wave.do ee762\ps8_list.do
Project Step 9 - Due Monday March 5th - ee762/PSsar.pdf CODE FILE: ee762\sar_tb.vhdl
.do files ee762/pssar_wave.do ee762/pssar_list.do
Project Step 10 - Due Friday May 30 - ee762/PS10.pdf
CODE Shell FILE FOR YOUR MODEL: ee762\fpm_your_model.vhdl
TESTVECTOR FILE: ee762\fpmvector
TESTBENCH CODE FILE: ee762\fpmtb.vhdl MODIFY TO ENTER YOURNAME
,do files ee762\fpm_list.do ee762\fpm_wave.do
Extra Credit Files: Extra Credit Due May 30 - Description ee762\PS Extra Credit.htm
Code FILE: ee762\pr_step_excr.vhdl
.do files ee762/excr_wave.do ee762/excr_list.do
Test bench seems to now be working. Updated over weekend and posted Tuesday May 27
Updated to here SP 08.
ASSIGNMENT SUMMARY TABLE
| STEP (2007 valid) | Aspect of Language Introduced |
| Project Step 1 x | The Generic Unit - DATAFLOW VHDL |
| Project Step 2 x | ALU Slice - 1st Structural Architecture |
| Project Step 3 x | 8 Bit ALU - Structural Hierachy |
| Project Step 4 x | 1st Behavioral Architecture for 8 Bit ALU |
| Project Step 5 | 2nd Behavioral Architecture - Procedures/Functions |
| Project Step 6 | 3rd Behavioral Architecture - Packages/abstraction |
| Project Step 7 | Register set - modeling of busses & multi-value logic |
| Project Step 8 | Multiple drivers on a bus. Modeling of a more complex architecture having an ALU and registers. Introduced the need for type conversion. |
| Project Step 9 | Sequential machine design with VHDL (A synthesis coding style for sequential design is introduced) |
| Project Step 10 | Floating Point Adder - use of libraries, use of packages without having access to the code |