Joanne E. DeGroat

Associate Professor
Electrical Engineering
The Ohio State University

Campus Address:
205 Dreese Laboratory
Department of Electrical Engineering
2015 Neil Avenue
Columbus, OH 43210 USA

phone: (614) 292-2439 (no answering machine)
fax: (614) 292-7596

cell (614) 595-1904
email: degroat.1@osu.edu

COURSE WEB PAGES

FALL 2009

ECE 261 MWF 8:30-9:30 Journalism 300 - Web page: ece_261__web_page.htm

ECE 765 MWF 1:30-2:30 CL137 : Web page ece765\ece_765.htm

Grad Schedule form: Grad Schedule Form.pdf

Spring 2009

H193 INFO

Sample report for an example H193/Tm Butterworth Proposal Draft (with cpright).pdf

Winter 2009

ECE 582 MWF 10:30-11:30 048 Scott

Web Page - ece582_web_page.htm

ECE 762 MWF 1:30-2:30 198 Baker Systems

Web page for ECE 762: EE762 Web Page

Fall 2008

ECE 764 M-W-F 10:30-11:30 260 Boles

Web Page for ECE 764: ece764_web_page.htm

ECE 561 M-W-F 12:30-1:30 412 Boles

Web Page for ECE 561: ece561_web_page.htm

Other Course Web Pages

EG167C: (LECTURES CAN BE FOUND AT EG167C Web Page)

Other online course materials

PE REVIEW SESSION - COMPUTER AREA SLIDES

Basics PE Review\Digital Systems Slides.pdf Example Problems: PE Review\Digital Systems Slides p2.pdf

Biography

Professor DeGroat received her Ph.D. in Electrical Engineering from the University of Illinois in 1991, her MS Electrical Engineering from Syracuse University in 1978, and a BS Engineering Science from Penn State in 1973. Professor DeGroat worked for Eastman Kodak Company in Rochester, New York before entering the US Air Force in 1974. While in the US Air Force she worked at Rome Air Development Center at Griffiss AFB, NY and at The Air Force Institute of Technology at Wright Patterson AFB. She came to OSU in 1990 and now teaches courses on computer design and VLSI. She helped develop and standardize the hardware description language, VHDL.

Research Interests

Dr. DeGroat's research interests are in the areas of Computer Architecture, VLSI, Electronic Design Automation, and Hardware/Software Codesign. Several research projects are currently underway in the Design Automation Research Lab (DARL).

A Past Project in the CAD area was:

VHDL Modeling of Architectural Building Blocks - To allow the rapid prototyping of application specific signal processors, an extensive VHDL library of architectural building blocks is needed. This library should include behavioral models of the off-the-shelf parts, as well as VHDL synthesizable models. The library can be used by hardware designers to develop and simulate behavioral models of signal processing systems, and then to use a synthesis system to automatically generate a circuit for the design.

"Hierarchical Extraction and Verification of Electronic Circuits" -

Publications and Societies

Area Under Construction.

Personal Interests

Area Under Construction.

JED 5/6/98