Research Interests
Low-voltage/Low-power VLSI Circuits
RF and Mixed Signal VLSI Circuits for Wireless Communications
Statistical Computer-aided Design and Optimization
Integrated Circuits for Image, Video and Multimedia Applications
VLSI Information Processing
Current and most recent research work in the Analog VLSI Lab focuses on:
-
Low Voltage, Low Power Analog and Mixed Signal VLSI in CMOS bipolar and BiCMOS technologies.
The work focuses on finding low power design solutions at both the system
and sub-system or block level. Examples include low voltage low power rail to rail
opamps and OTAs with constant gm, low power digitally programmable filters and variable
gain amplifiers and design techniques for low power wireless transceiver front ends
-
Circuits for Communication, RF CMOS,multimedia, Instrumentation, Sensors, Medical,
and Automotive Electronics
The work in this area is focusing on CMOS and BiCMOS chip design for a wide domain of applications. A project completed recently focused on the design of a CCD imager interface CMOS chip with a CDS, AGC and A/D converter for Camcoders. Many other projects were also completed for medical and automotive applications.
More recently, the research has been focusing on wireless telecommunication applications. The work involves finding low power cost effective design solutions for wireless transceivers, particularly in standard sub micron CMOS technologies. Recent projects include design of a WCDMA receiver chip set for cellular applications and a 433MHz FSK CMOS wireless chip set for home automation applications.
Ongoing and near term projects include chip design solutions for multi-standard wireless applictaions targeting TDMA standards(GSM and DECT) and CDMA standrads(ECDMA, CDMA2000, bluetooth and WLAN). The research spans the RF parts(LNAs,Mixers, I-Q generators and buffers), baseband parts including channel select filters, variable gain amplifiers and high speed data converters, and frequency synthesizers parts including design of low phase noise VCOs and PLLs. Several techniques are being explored to find cost effective chip design solutions achieving multi standards. This includes transceivers featuring digital programmability of the RF front ends.
-
Statistical Modeling, Simulation and Optimization of VLSI Circuits
The work in this area involves statistical modeling techniques to account for both inter- and intra-die variations with the goal of developing statistcal CAD tools which take into account layout information as well as device correlation.The work
helps optimize device sizes with the ultimate goal of enhancing the yield of analog
MOS ICs and minimizing yield loss due to the analog parts in a mixed signal chip.
A toolkit based on the SMOS model developed in this Lab in 1992 is currenly operational
and is fully integrated into the APLAC circuit simulator .
Statistical simulation is routinely used in this lab in both our research and educational activities .Most of our designs are statistically simulated and evaluated in terms of parameteric yield prior to fabrication in a specific technology.This adds to our program the important perspective on physical design issues pertaining to chip yield and robustness.
|
ismail@ee.eng.ohio-state.edu
