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The Ohio State University Course Syllabus |
| EE 734 |
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Spring 2001
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Prerequisites:
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EE 432 or permission of instructor |
| Course Objectives: | To teach the student processing technology used for fabrication of silicon VLSI integrated circuits. The primary focus will be on developing an understanding of process integration for NMOS, CMOS and MOS memory IC technology. |
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Text:
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James D. Plummer, Michael D. Deal, Peter B. Griffin, Silicon VLSI Technology – Fundamentals, Practice and Modeling, Prentice Hall, 2000, ISBN 0-13-085037-3 |
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Instructor:
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Prof. G.J. Valco, CL373, 292-5110, mailto:Valco.1@osu.edu |
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Topics:
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The primary focus will be on developing an understanding of process integration for NMOS, CMOS and MOS memory IC technology. Selected individual processing technologies will be covered in more depth. These may include silicon epitaxy, oxidation, lithography, plasma etching, chemical vapor deposition, diffusion, ion implantation and metal deposition. While all of these processes will be touched on, it is impossible to treat all of them in depth in one quarter. In class discussions and the relative importance of the individual processes for developing an understanding of process integration will be used as a guide to select those processes to be covered in more depth. |
| References: | S. Wolf and R.N. Tauber,Silicon Fabrication for the VLSI Era, Volume 1 - Silicon Processing, Lattice Press, 1986. |
| S.Wolf, Silicon Fabrication for the VLSI Era, Volume 2 - Process Integration, Lattice Press, 1990 | |
| S. Wolf, Silicon Fabrication for the VLSI Era, Volume 3 - The Submicron MOSFET, Lattice Press, 1995 | |
| Stephen A. Campbell, The Science and Engineering of Microelectronic Fabrication," Oxford University Press, 1996 or 2nd edition 2001 | |
| C.Y. Chang and S. M. Sze, ULSI Technology, McGraw Hill, 1996 | |
| S.K. Ghandhi, VLSI Fabrication Principles, Wiley, 2nd edition, 1994 | |
| S.M. Sze, VLSI Technology, 2nd ed., McGraw Hill, 1988. | |
| R.C. Jaeger, Introduction to Microelectronic Fabrication, Addison-Wesley, 1988 | |
| D.K. Reinhard, Introduction to Integrated Circuit Engineering, Houghton Mifflin Co., 1987 | |
| R. A. Colclaser, Microelectronics: Processing and Device Design, John Wiley and Sons, Inc., 1980 |
| GRADING: | Homework | 20% |
| 2 Midterms | 25% each | |
| Final Exam | 30% |
| Homework will be assigned in class. Some of the assignments will involve use of computers. All students enrolled in this class will have an account in the EE Computing Lab. |
| Late homework will be accepted until I publicize the solutions. A time-weighted penalty will be assessed. |
| All Exams will be closed book, closed notes. You will be allowed to bring one 8.5" x 11" sheet of equations (handwritten, not photocopied). I will also supply a sheet of needed equations and/or constants. Missed exams may not be made up unless you have a strong reason (i.e., serious illness, traffic accident on your way to the exam) with written documentation by an authority (i.e., doctor's note, copy of police report). |
| Final Exam Mon, June 4, 9:30 am -11:18 am. The final exam will be comprehensive. (Graduating students will have a third midterm exam during regular class hours on Wednesday, May 30, 1999. This exam will not be comprehensive.) |
| Honor Code: This course will be conducted in accordance with the OSU EE Honor Code. The EE Honor Code applies to all students enrolled in electrical engineering courses. (Copies of the honor code are available in the Electrical Engineering Department Office, 205 Dreese Lab). |