Distinguished Seminar: Prof. Natalie Enright Jerger from University of Toronto
Join Department of Electrical and Computer Engineering for a special seminar by Prof. Natalie Enright Jerger from University of Toronto.
Tuesday, April 16th, 2019 4-5 p.m
Dreese Lab 260 (Coffee and cookies provided)
Error-Ecient Architectures for Machine Learning
As Moore's Law continues in the post-Dennard scaling era, architects and programmers must consider energy efficiency even more carefully as part of their designs. Adding to these challenges is the continued rise of computationally-intensive applications, most notably machine learning. In recent years, advances in machine learning have unlocked the tremendous promise of these applications yet they require signi cantly more compute power than a orded by modern processors. In this talk, we explore how error-efficient architectural design can deliver higher performance for machine learning with lower energy consumption. Error-efficient design allows judicious introduction of errors at the microarchitectural level that yield answers that, while not 100% correct are acceptable for particular applications. Specifcally, I will present two recent projects applying this methodology. First, I will present a dedicated machine learning accelerator architecture, CNVLUTIN, that eliminates ineffectual and near ineffectual computation to improve throughput and avoid
wasted work. Second, I will explore error-efficiency in the context of energy harvesting internet-of-things (IoT) devices that operate on extremely constrained energy budgets. We propose to dynamically adjusting data precision to produce an acceptable output across a range of applications including machine learning, while dramatically improving performance. Through both of these projects, we demonstrate the promise of relaxing correctness to boost performance and energy-ecient in next-generation computer architectures.
Natalie Enright Jerger is the Percy Edward Hart Professor of Electrical and Computer Engineering at the University of Toronto. Prior to joining the University of Toronto, she received her MSEE and PhD from the University of Wisconsin-Madison in 2004 and 2008, respectively. She received her Bachelor's degree from Purdue University in 2002. She is a recipient of the Ontario Ministry of Research and Innovation Early Researcher Award in 2012, the 2014 Ontario Professional Engineers Young Engineer Medal recipient, the 2015 Borg Early Career Award winner, a Sloan Research Fellow and a Distinguished Member of the ACM. She served as the program chair of the 20th International Symposium on High Performance Computer Architecture. She is currently serving as the ACM SIGMICRO Vice Chair and an ACM SIGARCH Executive Committee member. Her current research explores on-chip networks, approximate computing, IoT architectures and machine learning acceleration. She is also passionate about increasing the representation of women in computing, particular in computer architecture. She currently chairs the organizing committee for the Women in Computer Architecture group (WICARCH). In 2017, she co-authored the second edition of the Computer Architecture Synthesis Lecture on On-Chip Networks with Li-Shiuan Peh and Tushar Krishna.